High-density interconnect boards compress more routing into smaller space, but that compression creates signal-integrity risk. A trace that is 75 µm wide behaves very differently from a 150 µm trace, and a 40 µm dielectric layer leaves almost no room for thickness variation. In automotive radar, medical imaging, telecom infrastructure, aerospace electronics and industrial control, impedance mismatch can produce jitter, reflection, crosstalk and unwanted electromagnetic interference. Design teams therefore need more than a generic PCB impedance calculator. They need a structured method for How to Calculate Impedance for HDI Boards that accounts for thin laminates, laser-drilled microvias, fine-line etching and sequential lamination.
Why HDI Stackups Change Impedance Calculations
HDI boards are not simply standard PCBs with smaller traces. They use microvias, buried vias and sequential lamination to achieve higher wiring density. The dielectric layers between copper planes are often only 25 µm to 75 µm thick, compared with 100 µm to 200 µm in conventional multilayer boards. That difference has a major impact on impedance because the distance between a trace and its reference plane is one of the most sensitive variables in the calculation. In a standard board, a ±10 µm variation on a 200 µm dielectric is only 5%. In an HDI board, the same ±10 µm variation on a 40 µm dielectric is 25%, which can shift a 50 Ω line to well above or below the target impedance. For high-speed differential pairs, this type of variation directly degrades the eye diagram and increases return loss.
Fine-line etching also changes the calculation. HDI designs commonly use trace widths and spacings of 50 µm to 100 µm, and fabricators must hold tight etching tolerances. A 10 µm etch change on a 75 µm trace is roughly 13% of the trace width, which is significant enough to alter the characteristic impedance. In addition, the copper thickness plays a larger relative role when the trace is narrow. Designers must therefore calculate impedance using the finished trace width rather than the nominal artwork width. The etch factor, plating thickness and surface finish should all be included in the effective geometry.
Microvia transitions introduce further impedance discontinuities. Although a laser-drilled microvia has lower parasitic inductance and capacitance than a larger through-hole via, the transition from a fine trace to a microvia capture pad, through the barrel, and into an inner layer still creates a localized impedance change. In dense HDI routing, multiple microvia transitions on a differential pair can produce mode conversion and reflection if the antipad size, capture pad diameter and return-path clearance are not optimized. Materials also matter. Resin-rich regions around laser-drilled microvias, glass-weave effects and thin prepregs can create local dielectric constant variations. This is why HDI impedance control must include stackup design, material selection and via geometry, not just a simple trace-width formula.
Core Formulas and Input Parameters for HDI Impedance Control
The starting point for single-ended impedance is the classic microstrip or stripline approximation. For a surface microstrip, the characteristic impedance can be estimated using the formula:
Z0 = (87 / √(Er + 1.41)) × ln(5.98h / (0.8w + t))
For a symmetric stripline, a common approximation is:
Z0 = (60 / √Er) × ln(4h / (0.67π(0.8w + t)))
In these formulas, Er is the dielectric constant, h is the dielectric height to the reference plane, w is the trace width, and t is the copper thickness. The equations give a useful starting point, but HDI boards require more careful inputs. The dielectric constant should be the value at the actual operating frequency, not the low-frequency datasheet value. The dielectric thickness must reflect the final pressed thickness after lamination, including resin flow. The trace width should be the finished width after etching and plating. The copper thickness must include base foil plus plated copper. For differential pairs, the impedance can be approximated using:
Zdiff ≈ 2 × Z0 × (1 – 0.48 × exp(-0.96 × s / h))
Here, s is the edge-to-edge spacing between the two traces. The spacing-to-dielectric-height ratio is especially important in HDI because thinner dielectrics force tighter spacing to maintain the same differential impedance. A 90 Ω or 100 Ω differential pair on a 50 µm dielectric may require a spacing of 60 µm to 80 µm, which pushes the fabricator’s etching and registration capabilities.
Several additional parameters affect the calculated impedance in HDI boards. Solder mask lowers the impedance slightly by increasing the effective dielectric constant around the trace. Copper roughness increases the effective resistance and can affect high-frequency impedance. Glass weave can create skew between the two halves of a differential pair if the traces land over resin-rich and glass-rich areas. Reference plane voids, such as those under BGA pads or split planes, alter the return path and change impedance locally. For dense HDI designs with arbitrary layer transitions, a 2D or 3D field solver is often required because simple formulas assume uniform cross-sections and uninterrupted reference planes.
A practical example helps clarify the numbers. Consider an HDI microstrip with a 50 µm dielectric height, a dielectric constant of 3.3, a finished trace width of 80 µm and copper thickness of 18 µm. Plugging these values into the microstrip formula gives a characteristic impedance of approximately 52 Ω. This is close to a 50 Ω target, but the designer would still need to adjust the trace width, dielectric thickness or solder mask thickness slightly for final tuning. More importantly, the fabricator must hold those values within tight tolerances across the panel. This is why HDI impedance calculation is an iterative process rather than a one-time equation.
Practical Workflow: Calculating and Validating Impedance in HDI Boards
A reliable HDI impedance calculation workflow starts with stackup acquisition. Design teams should request the fabricator’s actual pressed prepreg and core thicknesses, resin content, glass style, copper foil type and final dielectric constant after lamination. Datasheet values are not enough because the final thickness changes after pressing. For a medical wearable or aerospace rigid-flex HDI board, the stackup may also include polyimide or low-flow prepregs with different dielectric properties. The impedance target should be defined by the signaling standard: commonly 50 Ω single-ended and 90 Ω or 100 Ω differential for high-speed interfaces. Some memory or RF interfaces may require 40 Ω or 75 Ω.
Once the stackup is known, the next step is to calculate initial trace geometries using the formulas above or an impedance solver. The designer adjusts trace width, spacing, dielectric height and reference plane distance until the calculated values match the target. In HDI boards, trace width and spacing are often constrained by routing density. If the required trace width becomes too small or spacing too tight for the fabricator, the design may need a thinner dielectric or a different reference plane assignment. This is where HDI experience becomes critical. A small change in dielectric thickness can bring a 100 Ω differential pair back into tolerance without widening the routing channel.
After the initial calculation, the design must be validated at the transition points. Microvia transitions, BGA breakout regions and traces over plane splits should be modeled with a field solver. The antipad size on inner layers, the capture pad diameter and the unused via stub all influence the localized impedance. In sequential lamination HDI, blind vias can be kept short, which reduces stub effects. In high-frequency automotive or telecom boards, even a short microvia barrel can create a noticeable return-loss penalty if the return current cannot transition cleanly between reference planes. The return-path via should therefore be placed near each signal via, and the antipad should be tuned rather than left at default size.
Finally, the calculated impedance must be verified on a fabricated coupon. A proper HDI impedance coupon uses the same stackup, trace width, spacing, copper weight and solder mask as the production board. It should include both single-ended and differential test traces with launch pads for time-domain reflectometry. The fabricator measures the coupon and compares the results with the design targets. If the measured impedance is high, the trace width may need to be increased or the dielectric thickness reduced. If it is low, the opposite adjustment applies. This validation loop closes the gap between theory and production, ensuring that the HDI board performs as expected in automotive, medical, telecom, aerospace or industrial applications.
